1. Field of the Invention
The present invention relates generally to the reliability test of semiconductor integrated circuit chips and, more particularly, to an on-chip test circuit constructed at corners of an integrated circuit chip or die for assessing chip integrity.
2. Description of the Prior Art
Semiconductor manufacturers have been shrinking transistor size in integrated circuits (IC) to improve chip performance. This has resulted in increased speed and device density. For sub-micron technology, the RC delay becomes the dominant factor. To facilitate further improvements, semiconductor IC manufacturers have been forced to resort to new materials utilized to reduce the RC delay by either lowering the interconnect wire resistance, or by reducing the capacitance of the inter-layer dielectric (ILD). A significant improvement was achieved by replacing the aluminum (Al) interconnects with copper, which has ˜30% lower resistivity than that of Al. Further advances are facilitated by the change of the low-k dielectric materials.
However, one shortcoming associated with the use of low-k dielectrics is that almost all low-k dielectric materials possess relatively lower mechanical strength than that of conventional silicon oxide dielectrics such as FSG or USG. The use of low-k dielectrics poses this industry another problem that the adhesion ability, either at the interface between two adjacent low-k dielectric layers or at the interface between a low-k dielectric layer and a dissimilar dielectric layer, is somewhat inadequate to meet the requirements in the subsequent wafer treatment processes such as wafer dicing, which is typically performed to mechanically cut a semiconductor wafer into a number of individual IC chips.
Delamination or cracking that occurs during scribing, dicing or temperature cycling test is problematic and may cause circuit chip failures. One approach to monitoring of the interface delamination or chip cracking is so-called Scanning Acoustic Tomography (SAT) or Scanning Acoustic Microscopy (SAM) technique. The SAM technique, which can be implemented either after dicing (i.e., bare die check) or after chip packaging (i.e., packaged IC check), utilizes superimposed ultrasonic pulse and echo signals to detect the delamination or cracking defects formed in the integrated circuit chips or packages.
However, the SAM technique has some drawbacks. During the bare die check after dicing, very small cracks are difficult to detect because of the detection limit of the SAM tools. Typically, the detection limit of the commercial SAM tools is about 1 micrometer. On the other hand, even the delamination defect is detectable it is often difficult to characterize the specific location of the defect for the packaged IC check. That is, the information whether the defect is in the interlayer of the IC chip or at the interface between the IC chip and packaging material is not available.
Therefore, a need exists in this industry for a sensitive, but inexpensive approach to the detection of the delamination or cracking defects formed in the integrated circuit chips or packages.